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北京前端兼职程序员

ID：324578

Catherine喜洋洋

高级研发工程师

公司信息：
德州仪器

工作经验：
3年

兼职日薪：
500元/8小时

兼职时间：
下班后
周六
周日
可工作日远程

所在区域：
北京
海淀

技术能力

Languages: MATLAB, verilog, system verilog, python, perl, C++, linux shell, makefile

擅长语言：MATLAB, verilog, system verilog, python, perl, C++, linux shell, makefile 等

项目经验

MATLAB Simulation for Denoising the Electrocardiogram

This project focus on the analysis and simulation of denoising ECG by MATLAB. We first briefly introduce the biophysical mechanism of how heart generates electric impulses, then, we analyze the generation and simulation of ECG signals on PC, after the analysis, we design Butterworth filters for purifying the ECG signal for more accurate diagnosis, i.e, removing the Power Line Interference and Electrode Contact Noise. Finally, by comparing the FFT of ECG before and after filtering, we evaluated our filter performance.
编程语言： MATLAB

Binary Manipulation over HTTP via Man in the Middle Attack

Project description: Software is primarily distributed via the internet as bandwidth has increased along with the prevalence of software providers. The mechanisms for this delivery, however, are not always secure. Recent news stories [2] [12], have hinted at the potential ways in which downloads of executable files over HTTP connections may be modified en route. However, the literature shows a dearth of information on this subject. In this paper we explore methods for infiltrating executable files via the insertion of malicious code delivered through man in the middle attack. We explore the detectability of a tool capable of on the fly manipulation of binaries for multiple platforms. We determine that some countermeasures are more effective than others, in particular when they do not allow users to bypass their warning messages and instead refuse to run “damaged” binaries.

编程语言： Java

案例展示

基于 MPI 的多服务器时间校准(C++

there is a server A 10.10.70.200 and server tb 10.10.70.201: 1. record current timestamp TA[n-1](use RDTSC time counter), call GstRouterS
齐模式的 clock generator

上升沿对齐模式的 clock generator, 脉宽、周期任意变换（system verilog) 下降沿对齐模式的 clock generator, 脉宽、周期任意变换（system verilog) 上升沿&下降沿对齐模式的 clock generator,
基于 MPI 的多服务器时间校准(C++

there is a server A 10.10.70.200 and server tb: 1. record current timestamp TA[n-1](use RDTSC time counter), call GstRouterSend(GstRouter